A computer consists of a CPU and an I/O device $D$ connected to main memory $M$ via a shared bus with a data bus width of one word $(16-bits)$. The CPU can execute a maximum of $10^6$ instructions per second. An average instruction requires $five $ processor cycles, $three$ of which use the memory bus. A memory read or write operation uses $one$ processor cycle. Suppose that the CPU is continuously executing “background” programs that require $95$% of its instruction execution rate but not any I/O instructions. Now very large blocks of data are to be transferred between $M $ and $D$. Estimate the rate if DMA transfer is used.
P.S. Assume that one processor cycle equals one bus cycle. The answer says: $$10^6 * (0.05 * 5 + 0.95 * 2) = 2.15 * 10^6$$ Can someone explain the reasoning behind the answer ? I could understand that $0.05$ is percent of time devoted by CPU and $0.95$ is the percent of time devoted by DMA, but what about $5$ and $2$ ? If it has something to do with cycles, then I did not understand the logic.
Asked By : SimpleGuy
Answered By : SimpleGuy
The question says that on an average an instruction requires $5$ $cycles$ and the CPU is busy $95$% of the time in executing those instructions. Out of these $5 cycles$, $3 cycles$ are needed for memory operations. During this time $DMA$ cannot access the memory.
So only $2 cycles$ are left for $DMA$ to use for 95% of the time. For 95% time DMA uses $$0.95 * 2 cycles$$ For rest 5% time, CPU isn’t executing instructions, so all cycles are available, so DMA uses $$0.05 * 5 cycles$$ Total cycles available for DMA $$(0.05 * 5 + 0.95 * 2) cycles$$ In $1 second$, CPU can execute $10^6$ instructions. So rate of transfer is $$ 10^6 * (0.05 * 5 + 0.95 * 2) = 2.15 * 10^6 $$
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Question Source : http://cs.stackexchange.com/questions/35722
